DocumentCode
1327861
Title
A non-local impact ionization/lattice temperature model for VLSI double-gate ultrathin SOI NMOS devices
Author
Su, Ker-Wie ; Kuo, J.B.
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
44
Issue
2
fYear
1997
fDate
2/1/1997 12:00:00 AM
Firstpage
324
Lastpage
330
Abstract
This paper presents an analytical drain current model for VLSI double-gate ultrathin SOI NMOS devices considering both the nonlocal impact ionization effect and the lattice temperature effect. Supported by the experimental data, the analytical model predicts that the double-gate SOI NMOS device has a more obvious nonlocal impact ionization effect and a higher lattice thermal effect as compared to the single-gate device
Keywords
MOS integrated circuits; VLSI; impact ionisation; integrated circuit modelling; silicon-on-insulator; VLSI; double-gate ultrathin SOI NMOS devices; drain current model; lattice temperature effect; lattice thermal effect; nonlocal impact ionization effect; nonlocal impact ionization/lattice temperature model; Analytical models; Electric resistance; Impact ionization; Lattices; MOS devices; Semiconductor thin films; Silicon; Temperature; Thermal resistance; Very large scale integration;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.557726
Filename
557726
Link To Document