Design of the output-capacitorless low-dropout regulator for nano-second transient response

Low-dropout voltage regulators (LDOs) have been widely used in the mobile electronic devices. Owing to the energy saving purpose, LDOs are required to perform fast-transient response with low quiescent current as they operate at low supply voltage condition. Generally, designing the high gain operational amplifier is more challenging under the low supply voltage. The situation would be more complex when the ultra fast-transient response of the LDO is preferred in the design specification. This study proposes a LDO that adopts cascading technique using `multipath nested Miller compensation` for solving the low supply voltage problem. To further improve the transient response, a full quiescent current enhancement circuit is supplemented to the LDO control loop. Compared with the other dynamic bias approaches, the proposed technique raises the quiescent current to the maximum quantity during the load transient so that the load response of the LDO is further improved. Systematic analyses show that the stability is guaranteed. The designed LDO was implemented by a 0.35-μm complementary metal-oxide-semiconductor (CMOS) process. Test results show that the voltage spike under the 50-mA load change within 300 ns is improved `62% compared to that of the LDO without the proposed circuit. The recovery time is less than 1 μs.