Title :
Dual Read Method by Capacitance Coupling Effect for Mode-Disturbance-Free Operation in Channel-Recessed Multifunctional Memory
Author :
Park, Jin-Kwon ; Cho, Won-Ju
Author_Institution :
Dept. of Electron. Mater. Eng., Kwangwoon Univ., Seoul, South Korea
Abstract :
A channel-recessed multifunctional memory (MFM) device was investigated, and a dual read method using a capacitance coupling effect was developed. The nonvolatile memory (NVM) cells using a SiO2/Si3N4/SiO2 gate insulator and the high-speed single-transistor dynamic random access memory (1T-DRAM) cells using a floating-body effect of an SOI substrate were demonstrated in the single-channel-recessed MFM cells. In order for the layer to avoid the interference of operations between NVM and 1T-DRAM modes, a dual read method using the capacitance coupling effect between a front-gate oxide layer and a back-gate oxide was examined. As a result, a large memory window of NVM operation was accomplished by using the back-gate read operation. Furthermore, the reliability of both NVM and 1T-DRAM operations was improved, and the interferences of operation mode between NVM and 1T-DRAM were effectively suppressed.
Keywords :
capacitance; interference (signal); random-access storage; reliability; silicon compounds; silicon-on-insulator; 1T- DRAM cells; 1T-DRAM operation; MFM device; NVM cells; NVM operation; SOI substrate; Si; SiO2-Si3N4-SiO2; back-gate oxide; back-gate read operation; capacitance coupling effect; channel-recessed multifunctional memory; dual read method; floating-body effect; front-gate oxide layer; gate insulator; high-speed single-transistor dynamic random access memory; memory window; mode-disturbance-free operation; nonvolatile memory cells; single-channel-recessed MFM cells; Capacitance; Impact ionization; Nonvolatile memory; Random access memory; Silicon on insulator technology; Threshold voltage; Capacitorless; Fowler–Nordheim (FN) tunneling; SOI; dual read; impact ionization; multifunctional memory (MFM); single-transistor dynamic random access memory (1T-DRAM); threshold voltage;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2012.2218568