• DocumentCode
    1328305
  • Title

    Handling borders in systolic architectures for the 1-D discrete wavelet transform for perfect reconstruction

  • Author

    Ferretti, Marco ; Rizzo, Davide

  • Author_Institution
    Dipt. di Inf. e Sistemistica, Pavia Univ., Italy
  • Volume
    48
  • Issue
    5
  • fYear
    2000
  • fDate
    5/1/2000 12:00:00 AM
  • Firstpage
    1365
  • Lastpage
    1378
  • Abstract
    We propose a modified systolic architecture that implements the 1-D discrete wavelet transform (DWT) on the basis of the recursive pyramid algorithm (RPA) while correctly managing the border problem and obtaining perfect reconstruction. All the architectures so far described in the literature do not explicitly address the handling of borders and usually assume a zero-padding extension. The RPA makes heavy use of this assumption, which produces very efficient systolic architectures. It is, however, well known that the zero-padding extension does not allow perfect recovery of the original signal, if we compute exactly N coefficients. More coefficients are required either in the forward or in the inverse transform, and their production within the RPA scheme lowers the efficiency of the systolic architecture to a minimum. We introduce a modified RPA working on an extended transform with a compressed schedule that restores good values of efficiency (EC-RPA). We also propose a second version of RPA based on a periodic extension of the signal and of the transform (PE-RPA) that achieves perfect reconstruction by computing exactly N DWT coefficients. A reduced version of the second algorithm (R-PE-RPA) is tailored to the efficient computations of a fixed number of levels in the transform. The VLSI complexity of the management of borders is analyzed through synthesis from a VHDL description of the three algorithms. Synthesis results show that the controller required for PE-RPA can be as large as a ten-tap array. R-PE-RPA instead requires half this area. In both cases, the controller complexity scales sublinearly with the length of the input
  • Keywords
    VLSI; digital signal processing chips; discrete wavelet transforms; image reconstruction; parallel algorithms; systolic arrays; 1D discrete wavelet transform; DWT coefficients; VHDL description; VLSI complexity; border problem management; controller complexity; efficiency; extended transform; forward transform; input length; inverse transform; modified systolic architecture; perfect reconstruction; periodic extension; recursive pyramid algorithm; still images; synthesis results; zero-padding extension; Computer architecture; Discrete wavelet transforms; Image coding; Image reconstruction; Signal processing algorithms; Signal resolution; Signal synthesis; Systolic arrays; Very large scale integration; Wavelet transforms;
  • fLanguage
    English
  • Journal_Title
    Signal Processing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1053-587X
  • Type

    jour

  • DOI
    10.1109/78.839983
  • Filename
    839983