• DocumentCode
    1328394
  • Title

    VLSI implementation of a second-order digital filter

  • Author

    Sunder, Sanjay ; El-Guibaly, F. ; Antoniou, Athanasios

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
  • Volume
    19
  • Issue
    3
  • fYear
    1994
  • fDate
    7/1/1994 12:00:00 AM
  • Firstpage
    143
  • Lastpage
    147
  • Abstract
    The implementation of a second-order digital filter is discussed. A novel multiplier, by means of which an inner product operation is performed without the use of an accumulator, is used as a component in the second-order filter to achieve significantly reduced area and noise. In this multiplier, maximum use is made of all the cells comprising the multiplier.
  • Keywords
    VLSI; digital arithmetic; digital filters; multiplying circuits; VLSI; inner product operation; multiplier cells; novel multiplier; second-order digital filter; Adders; Delays; Digital filters; Limit-cycles; Logic gates; Quantization (signal); Registers;
  • fLanguage
    English
  • Journal_Title
    Electrical and Computer Engineering, Canadian Journal of
  • Publisher
    ieee
  • ISSN
    0840-8688
  • Type

    jour

  • DOI
    10.1109/CJECE.1994.6593846
  • Filename
    6593846
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1328394