DocumentCode :
1328883
Title :
A microprocessor based decoder for BCH codes
Author :
Le-Ngoc, Tho ; Bhargava, V.K.
Author_Institution :
Dept. of Electrical Dev. Engng., SPAR Aerospace, Que., Canada
Volume :
4
Issue :
4
fYear :
1979
Firstpage :
29
Lastpage :
32
Abstract :
Presents some preliminary results on the implementation of a binary BCH decoder involving a combination of specially designed hardware for some operations and a software implementation on a microprocessor for the remaining operations. With such a microprocessor based decoder, a large number of different BCH codes can be accommodated with little or no hardware changes. The decoding task is a function of the software and thus allows common hardware to support a wide range of functions. The main purpose of this paper is to report on the implementation of the error locator polynomial, and the Chien´s search for finding the error locations, using the table look-up technique suitable to a microprocessor based decoder.
Keywords :
decoding; digital circuits; error correction codes; microcomputers; BCH codes; binary BCH decoder; error correction codes; error locator polynomial; implementation; microprocessor based decoder; preliminary results; software implementation; specially designed hardware; Decoding; Finite element analysis; Galois fields; Hardware; Microprocessors; Polynomials; Software;
fLanguage :
English
Journal_Title :
Electrical Engineering Journal, Canadian
Publisher :
ieee
ISSN :
0700-9216
Type :
jour
DOI :
10.1109/CEEJ.1979.6593933
Filename :
6593933
Link To Document :
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