DocumentCode :
1329010
Title :
CMOS sense amplifier-based flip-flop with two N-C2MOS output latches
Author :
Kim, Jin-Cheon ; Jang, Young-Chan ; Park, Hong-June
Author_Institution :
Dept. of Electr. Eng., Pohang Inst. of Sci. & Technol., South Korea
Volume :
36
Issue :
6
fYear :
2000
fDate :
3/16/2000 12:00:00 AM
Firstpage :
498
Lastpage :
500
Abstract :
By replacing the NAND SR latch at the output stage of a conventional sense amplifier-based flip-flop (SAFF) by two N-C2 MOS latches, the operating speed of the flip-flop is enhanced by 63%, and the power-delay-product is reduced by 28%
Keywords :
CMOS logic circuits; CMOS sense amplifier-based flip-flop; N-C2MOS output latches; operating speed enhancement; power-delay-product reduction; synchronous CMOS VLSI chips;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:20000409
Filename :
840126
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=1329010
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