• DocumentCode
    1329017
  • Title

    Concentrator circuit with multiple priority levels

  • Author

    Krishnamoorthy, A.V. ; Lih-Yih Chiou ; Rozier, R.G. ; Kibar, O.

  • Author_Institution
    AT&T Bell Labs., Holmdel, NJ, USA
  • Volume
    36
  • Issue
    6
  • fYear
    2000
  • fDate
    3/16/2000 12:00:00 AM
  • Firstpage
    500
  • Lastpage
    501
  • Abstract
    The architecture is presented of a memory-less CMOS packet concentrator that carries out dynamic statistical multiplexing of data from N inputs to L outputs with multiple priority levels. Results are presented from a 16-channel test chip built using 0.5 μm CMOS technology
  • Keywords
    CMOS digital integrated circuits; line concentrators; packet switching; 0.5 micron; 16-channel test chip; CMOS packet concentrator circuit; dynamic statistical multiplexing; memory-less packet concentrator architecture; multiple priority levels;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20000287
  • Filename
    840127
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1329017