DocumentCode
1329030
Title
Reliable analysis of settling errors in SC integrators: application to ΣΔ modulators
Author
del Rio, R. ; Medeiro, F. ; Pérez-Verdú, B. ; Rodríguez-Vazquez, A.
Author_Institution
Inst. de Microelectron., Seville Univ., Spain
Volume
36
Issue
6
fYear
2000
fDate
3/16/2000 12:00:00 AM
Firstpage
503
Lastpage
504
Abstract
A study is presented into the transient response of SC integrators considering amplifier finite bandwidth, slew-rate, and parasitic capacitors during, unlike previous models, both the integration and sampling phases. The model is validated by experimental results on a second-order ΣΔ modulator and provides more reliable estimations of the defective settling in high-speed designs than previously reported models
Keywords
error analysis; integrating circuits; sigma-delta modulation; signal sampling; switched capacitor networks; transient analysis; transient response; ΣΔ modulator application; SC integrators; amplifier finite bandwidth; defective settling; high-speed designs; integration phase; parasitic capacitors; sampling phase; second-order ΣΔ modulator; settling errors; slew rate; transient response;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20000443
Filename
840129
Link To Document