DocumentCode
1329154
Title
Total Performance of 32-nm-Node Ultralow- 
/Cu Dual-Damascene Interconnects Featuring Short-TAT Silylated Porous Silica  silylated scalable porous silica (Po-SiO, <i>k</i> = 2.1) with high porosity (50%) is demonstrated. The TAT for the film formation process including silylation treatment is about 25% reduced by adding a promoter, causing reinforcement of the film. Applying this improved Po-SiO, a 140-nm-pitch dual-damascene structure is successfully achieved. The wiring capacitance showed 10% reduction, compared to the conventional porous SiOC (ULK, <i>k</i> = 2.65). Sufficient interconnect reliability and packaging characteristics for the circuit-under-pad structure are also obtained. The predicted circuit performance was 8% higher than ULK in the 32-nm node.</div></div>
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<div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Keywords</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; low-k dielectric thin films; circuit-under-pad structure; dual-damascene interconnects; film formation process; high porosity; interconnect reliability; packaging characteristics; short-TAT silylated scalable porous silica; silylation treatment; size 140 nm; size 32 nm; turnaround-time; ultralow-k interconnects; wiring capacitance; Capacitance; Copper; Integrated circuit interconnections; Reliability; Resistance; Wiring; Copper; interconnections; low-<formula formulatype=)
$k$ dielectric; porous silica;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2010.2066568
Filename
5580039
Link To Document