Title :
Low power flip-flop with clock gating on master and slave latches
Author :
Strollo, A.G.M. ; Caro, D. De
Author_Institution :
Dept. of Electron. & Telecommun. Eng., Naples Univ., Italy
fDate :
2/17/2000 12:00:00 AM
Abstract :
A new flip-flop is presented in which power dissipation is reduced by deactivating the clock signal on both the master and slave latches when there are no data transitions. The new circuit overcomes the clock duty-cycle constraints of previously proposed gated flip-flops. The power consumption of the presented circuit is significantly lower than that of a conventional flip-flop when the D input has a reduced switching activity
Keywords :
flip-flops; integrated logic circuits; low-power electronics; timing; D input; clock duty-cycle constraints; clock gating; clock signal deactivating; low power flip-flop; master latches; power dissipation reduction; reduced switching activity; slave latches;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20000268
