DocumentCode
1329707
Title
Very high-speed sigma-delta fractional-N synthesiser
Author
Brennan, P.V. ; Walkington, R. ; Borkjak, A. ; Thompson, I.
Author_Institution
Dept. of Electron. & Electr. Eng., Univ. Coll. London, UK
Volume
36
Issue
4
fYear
2000
fDate
2/17/2000 12:00:00 AM
Firstpage
298
Lastpage
300
Abstract
A new method for implementing a sigma-delta fractional-N synthesiser is described. Results demonstrate that a substantial improvement in performance is possible and that the synthesiser is capable of meeting the digital cellular system (DCS) base station specification
Keywords
sigma-delta modulation; DCS; PLL; base station specification; digital cellular system; sigma-delta fractional-N synthesiser;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20000059
Filename
840219
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