DocumentCode :
1329837
Title :
Monolayer 
Transistors Beyond the Technology Road Map
Author :
Alam, Khairul ; Lake, Roger K.
Author_Institution :
Dept. of Electr. & Electron. Eng., East West Univ., Dhaka, Bangladesh
Volume :
59
Issue :
12
fYear :
2012
Firstpage :
3250
Lastpage :
3254
Abstract :
The performance of a 5-nm gate length monolayer MoS2 transistor is benchmarked against an ultrathin body Si transistor of similar dimensions and the ITRS requirements for 2026 low operating power (LOP) technology. The MoS2 transistor has a subthreshold slope of 70 mV/dec, an on -/off-current ratio of 4.8 × 104, a drive current of 238 μA/μm, a peak transconductance of 2.65 mS/μm, a total capacitance of 0.164 fF/μm, and an intrinsic switching delay of 0.276 ps. These numbers for the silicon competitor are 79 mV/dec, 1.8 × 104, 89 μA/μm, 1.22 mS/μm, 0.0733 fF/μm , and 0.331 ps, respectively. The heavier effective mass of the MoS2 significantly reduces the direct source-drain leakage current, and it increases the drive current and the transconductance. The performance metrics of MoS2 transistor are comparable to the ITRS 2026 LOP technology requirements.
Keywords :
capacitance; effective mass; insulated gate field effect transistors; leakage currents; molybdenum compounds; monolayers; 2026 low operating power technology; ITRS 2026 LOP technology requirement; MoS2; capacitance; effective mass; gate length monolayer transistor; intrinsic switching delay; silicon competitor; size 5 nm; source-drain leakage current; technology road map; transconductance; Effective mass; FETs; Logic gates; Quantum capacitance; Silicon; Field effect transistors; monolayer $( hbox{MoS}_{2})$
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2012.2218283
Filename :
6343227
Link To Document :
