Title :
Comments on “New single-clock CMOS latches and flip-flops with improved speed and power savings”
Author_Institution :
Dept. of Electr. Eng., Edinburgh Univ., UK
fDate :
10/1/1997 12:00:00 AM
Abstract :
For original paper see J. Yuan and C. Svensson, ibid., vol.32, pp.62-69 (1997). In a recent paper, Yuan and Svensson propose various single-clock differential flip-flops; however, those using a dynamic slave are unsafe in the presence of input glitches. Further, a double-edge triggered flip-flop is developed from one of the semistatic versions
Keywords :
CMOS logic circuits; flip-flops; differential flip-flop; double-edge triggered flip-flop; dynamic slave; input glitch; latch; power consumption; single-clock CMOS circuit; speed; CMOS logic circuits; CMOS technology; Capacitance; Circuit synthesis; Clocks; Flip-flops; Latches; Master-slave; Solid state circuits; Switches;
Journal_Title :
Solid-State Circuits, IEEE Journal of
