• DocumentCode
    1331307
  • Title

    Power-conscious scheduling algorithm for performance-driven datapath synthesis

  • Author

    Lee, Jhih-Shian ; Lee, Hae-Dong ; Park, C.-W. ; Hwang, S.-Y.

  • Author_Institution
    Dept. of Electron. Eng., Sogang Univ., Seoul
  • Volume
    32
  • Issue
    17
  • fYear
    1996
  • fDate
    8/15/1996 12:00:00 AM
  • Firstpage
    1574
  • Lastpage
    1576
  • Abstract
    A power-conscious scheduling algorithm for the synthesis of datapaths with low power consumption is described. The proposed algorithm schedules operations so that switching activity can be minimised at functional modules. Experimental results confirm the efficiency of the proposed algorithm
  • Keywords
    CMOS digital integrated circuits; integrated circuit design; modules; scheduling; CMOS; algorithm efficiency; area constraints; functional modules; performance-driven datapath synthesis; power consumption; power-conscious scheduling algorithm; switching activity;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19961074
  • Filename
    533300
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1331307