Separate Extraction of Source, Drain, and Substrate Resistances in MOSFETs With Parasitic Junction Current Method

The separate extraction of asymmetric source (R_S) and drain (R_D) resistances caused by the variations in the layout, process, and device degradation is important in the practical modeling and characterization of MOSFETs and their integrated circuits. We propose a simple “parasitic junction current method” (PJCM) for the separate extraction of R_S, R_D, and R_SUB (substrate resistance) in MOSFETs. We applied the proposed PJCM to n-channel MOSFETs with different W/L combinations and verified its usefulness in the robust extraction of R_S, R_D, and R_SUB.