• DocumentCode
    1331693
  • Title

    Design of 25-nm SALVO PMOS devices

  • Author

    Vuong, H.H. ; Chang, C.P. ; Pai, C.S.

  • Author_Institution
    Bell Labs., Lucent Technol., Murray Hill, NJ, USA
  • Volume
    21
  • Issue
    5
  • fYear
    2000
  • fDate
    5/1/2000 12:00:00 AM
  • Firstpage
    248
  • Lastpage
    250
  • Abstract
    The concept and preliminary designs of novel self-aligned local-channel V-gate by optical lithography (SALVO) devices are presented. SALVO uses optimized local-channel doping to sharpen the lateral junctions, in order to minimize short channel effects for gate lengths down to 25 nm. In addition, it utilizes the replacement-gate design with inner spacers to facilitate integration of alternative gate stack materials and to extend the application of optical lithography. SALVO PMOS designs with both metal gate and poly-metal gate electrodes were studied, the latter proving capable of delivering high performance 25 nm PMOS with currently manufacturable processes.
  • Keywords
    CMOS integrated circuits; MOSFET; doping profiles; ion implantation; nanotechnology; photolithography; rapid thermal annealing; 25 nm; RTA; SALVO PMOS devices; channel implant partitioning; gate length; gate stack materials; lateral junctions; metal gate electrodes; optimized local-channel doping; poly-metal gate electrodes; polysilicon gate; replacement-gate design; self-aligned local-channel V-gate by optical lithography; short channel effect minimization; Design optimization; Doping profiles; Electrodes; Implants; Lithography; MOS devices; Optical design; Optical devices; Optical scattering; Rapid thermal annealing;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/55.841311
  • Filename
    841311