Ultrathin-body SOI MOSFET for deep-sub-tenth micron era

Author

Choi, Yang-Kyu ; Asano, Kazuya ; Lindert, Nick ; Subramanian, Vivek ; King, Tsu-Jae ; Bokor, Jeffrey ; Hu, Chenming

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

21

Issue

5

fYear

2000

fDate

5/1/2000 12:00:00 AM

Firstpage

254

Lastpage

255

Abstract

A 40-nm-gate-length ultrathin-body (UTB) nMOSFET is presented with 20-nm body thickness and 2.4-nm gate oxide. The UTB structure eliminates leakage paths and is an extension of a conventional SOI MOSFET for deep-sub-tenth micron CMOS. Simulation shows that the UTB SOI MOSFET can be scaled down to 18-nm gate length with <5 nm UTB. A raised poly-Si S/D process is employed to reduce the parasitic series resistance.

Keywords

CMOS integrated circuits; MOSFET; nanotechnology; semiconductor device measurement; silicon-on-insulator; work function; 18 nm; 2.4 nm; 20 nm; 40 nm; I-V characteristics; SiO/sub 2/-SiGe-SiO/sub 2/-Si; body thickness; deep-sub-tenth micron CMOS; gate length; gate oxide; gate work function engineering; leakage path elimination; parasitic series resistance; raised poly-Si S/D process; short channel effect suppression; simulation; ultrathin-body SOI MOSFET; ultrathin-body nMOSFET; Doping profiles; Etching; Fabrication; Germanium silicon alloys; Immune system; MOSFET circuits; Plasma temperature; Resists; Silicon germanium; Silicon on insulator technology;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.841313

Filename

841313