Precise delay generation using the Vernier technique

The authors show a new technique for generating precise clock delays. The Vernier technique exploits the difference between two coarse delays to achieve delay resolutions much smaller than an intrinsic gate delay. This resolution limit is usually smaller than a conventional gate delay, the limit for most conventional delay generation methods. The Vernier technique has the additional advantage of being easy to implement. Simulations show that this technique is capable of resolutions as small as 50 ps using 2.0 μm CMOS