Title :
A 144-Mb, eight-level NAND flash memory with optimized pulsewidth programming
Author :
Nobukata, Hiromi ; Takagi, Shunsuke ; Hiraga, Keizo ; Ohgishi, Takeshi ; Miyashita, Masaru ; Kamimura, Kazuto ; Hiramatsu, Shinji ; Sakai, Kiyohisa ; Ishida, Takahiro ; Arakawa, Hideki ; Itoh, Masahiko ; Naiki, Ihachi ; Noda, Masanori
Author_Institution :
Memory Dept., Sony Corp. Core Technol. & Network Co., Tokyo, Japan
fDate :
5/1/2000 12:00:00 AM
Abstract :
We report a fast-programming, compact sense and latch (SL) circuit to realize an eight-level NAND flash memory. Fast programming is achieved by supplying optimized voltage and pulsewidth to the bit lines, according to the programming data. As a result, all data programming is completed almost simultaneously, and 0.67-MB/s program throughput, which is 1.7 times faster than conventional program throughput, is achieved. The compact layout of the SL circuit is made possible by four 3-bit latches sharing one unit of the read/verify control circuit. Using these techniques, we fabricated a 144-Mb, eight-level NAND flash memory using a 0.35-/spl mu/m CMOS process, resulting in a 104.2-mm/sup 2/ die size and a 1.05-/spl mu/m/sup 2/ effective cell size.
Keywords :
CMOS memory circuits; NAND circuits; PLD programming; cellular arrays; flash memories; 0.35 micron; 144 Mbit; CMOS process; bit lines; data programming; die size; effective cell size; eight-level NAND flash memory; optimized pulsewidth programming; read/verify control circuit; sense and latch circuit; CMOS process; Digital audio players; Digital cameras; Large scale integration; Latches; Pulse circuits; Space vector pulse width modulation; Threshold voltage; Throughput; Voltage control;
Journal_Title :
Solid-State Circuits, IEEE Journal of
