Title :
A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs
Author :
Hoenigschmid, Heinz ; Frey, Alexander ; DeBrosse, John K. ; Kirihata, Toshiaki ; Mueller, Gerhard ; Storaska, Daniel W. ; Daniel, Gabriel ; Frankowsky, Gerd ; Guay, Kevin P. ; Hanson, David R. ; Hsu, Louis Lu-Chen ; Ji, Brian ; Netis, Dmitry G. ; Panaroni
Author_Institution :
IBM Semicond. Res. & Dev. Center, Infineon Technol., Hopewell Junction, NY, USA
fDate :
5/1/2000 12:00:00 AM
Abstract :
A 7F/sup 2/ DRAM trench cell and corresponding vertically folded bitline (BL) architecture has been fabricated using a 0.175 /spl mu/m technology. This concept features an advanced 30/spl deg/ tilted array device layout and an area penalty-free inter-BL twist. The presented scheme minimizes local well noise by maximizing the number of twisting intervals. A significant improvement of signal margin was measured on a 32-Mbyte test chip.
Keywords :
DRAM chips; cellular arrays; integrated circuit noise; isolation technology; memory architecture; 0.175 micron; 4 Gbit; 7F/sup 2/ cell; DRAMs; bitline architecture; local well noise; penalty-free vertical BL twists; signal margin; tilted array devices; trench cell; twisting intervals; vertically folded bitline; Capacitors; Random access memory; Research and development; Semiconductor device measurement; Semiconductor device noise; Testing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
