DocumentCode
1332213
Title
Accurate X-Propagation for Test Applications by SAT-Based Reasoning
Author
Kochte, Michael A. ; Elm, Melanie ; Wunderlich, Hans-Joachim
Author_Institution
Inst. of Comput. Archit. & Comput. Eng., Univ. of Stuttgart, Stuttgart, Germany
Volume
31
Issue
12
fYear
2012
Firstpage
1908
Lastpage
1919
Abstract
Unknown or X-values during test applications may originate from uncontrolled sequential cells or macros, from clock or A/D boundaries, or from tristate logic. The exact identification of X-value propagation paths in logic circuits is crucial in logic simulation and fault simulation. In the first case, it enables the proper assessment of expected responses and the effective and efficient handling of X-values during test response compaction. In the second case, it is important for a proper assessment of fault coverage of a given test set and consequently influences the efficiency of test pattern generation. The commonly employed n-valued logic simulation evaluates the propagation of X-values only pessimistically, i.e., the X-propagation paths found by n -valued logic simulation are a superset of the actual propagation paths. This paper presents an efficient method for overcoming this pessimism and for determining accurately the set of signals that carry an X-value for an input pattern. As examples, it investigates the influence of this pessimism on the two applications, X-masking and stuck-at fault coverage assessment. The experimental results on benchmark and industrial circuits assess the pessimism of classic algorithms and show that these algorithms significantly overestimate the signals with X-values. The experiments show that overmasking of test data during test compression can be reduced by an accurate analysis. In stuck-at fault simulation, the coverage of the test set is increased by the proposed algorithm without incurring any overhead.
Keywords
circuit reliability; circuit simulation; fault diagnosis; logic testing; sequential circuits; A/D boundary; SAT-based reasoning; X-masking; X-value propagation paths; fault simulation; industrial circuits; logic circuits; n-valued logic simulation; stuck-at fault coverage assessment; test compression; test data overmasking; test pattern generation; test response compaction; test set; tristate logic; uncontrolled sequential cells; Algorithm design and analysis; Failure analysis; Logic circuits; Simulation; Accurate fault simulation; simulation pessimism; stuck-at fault coverage; unknown values;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2012.2210422
Filename
6349431
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