An ECL-compatible GaAs SCFL design method

Author

Shimizu, Shoichi ; Yoshihara, Kunio ; Terada, Toshiyuki ; Ishida, Kenji ; Kitaura, Yoshiaki ; Takubo, Chiaki

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

25

Issue

2

fYear

1990

fDate

4/1/1990 12:00:00 AM

Firstpage

539

Lastpage

545

Abstract

A source-coupled FET logic (SCFL) circuit design method which provides compatibility with emitter-coupled logic (ECL) in terms of power supply voltage and logic level is described. The method considers device parameter variations (ΔV_th, ΔR, and ΔK), and changes in the ambient temperature. A -0.2 V threshold voltage (V_th), a 0.9-V logic swing voltage (V_SW), and a 0.35-V noise margin voltage (V_nm) were obtained to achieve compatibility with the ECL 10 K series power supply voltage of -5.2 V. A 5-Gb/s as well as a 3-Gb/s operational 4-b multiplexer and demultiplexer IC have been developed using this circuit design method

Keywords

III-V semiconductors; field effect integrated circuits; gallium arsenide; integrated logic circuits; logic design; 0.2 to 0.9 V; 10 K series; 3 Gbit/s; 5 Gbit/s; ECL-compatible; GaAs; SCFL design method; ambient temperature variations; device parameter variations; emitter-coupled logic; logic level; logic swing voltage; multiplexer/demultiplexer IC; noise margin voltage; power supply voltage; source-coupled FET logic; threshold voltage; Circuit synthesis; Design methodology; FETs; Gallium arsenide; Integrated circuit noise; Logic circuits; Logic design; Logic devices; Power supplies; Threshold voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.52182

Filename

52182