DocumentCode :
1332536
Title :
A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash–SAR Architecture
Author :
Young-Deuk Jeon ; Jae-Won Nam ; Kwi-Dong Kim ; Tae Moon Roh ; Jong-kee Kwon
Author_Institution :
Convergence Components & Mater. Res. Lab., Electron. & Telecommun. Res. Inst., Daejeon, South Korea
Volume :
59
Issue :
11
fYear :
2012
Firstpage :
741
Lastpage :
745
Abstract :
This brief presents a 10-bit dual-channel pipelined flash-successive approximation register (SAR) analog-to-digital converter (ADC) for high-speed applications. The proposed ADC consists of two channels for high operating speed, and each channel adopts a pipelined flash-SAR architecture for low power and a small area. The proposed flash-SAR ADC in the second stage is composed of a 1-bit flash ADC and a 6-bit SAR ADC considering the chip area, operation speed, and circuit complexity. The prototype ADC fabricated in a 45-nm CMOS process occupies 0.16 mm2. The differential and integral nonlinearities of the ADC are less than 0.36 and 0.67 LSB, respectively. The ADC shows a signal-to-noise-and-distortion ratio of 54.6 dB and a spurious-free dynamic range of 64.0 dB with a 78-MHz input at 230 MS/s with a 1.1-V supply. The maximum operating frequency of the ADC is 260 MS/s at a 1.2-V supply. The power consumptions of the ADC with 230 and 260 MS/s are 13.9 and 17.8 mW, respectively.
Keywords :
CMOS integrated circuits; analogue-digital conversion; circuit complexity; CMOS process; analog-to-digital converter; chip area; circuit complexity; differential nonlinearities; dual-channel pipelined ADC; flash-SAR architecture; flash-successive approximation register; frequency 78 MHz; high-speed applications; integral nonlinearities; operation speed; power 13.9 mW; power 17.8 mW; signal-to-noise-and-distortion ratio; size 45 nm; spurious-free dynamic range; sub-ADC; voltage 1.1 V; voltage 1.2 V; word length 1 bit; word length 10 bit; word length 6 bit; Ash; CMOS integrated circuits; Capacitors; Clocks; Generators; Solid state circuits; Switches; Analog-to-digital converter (ADC); flash; operational amplifier (op-amp) sharing; pipelined; reference buffer; successive approximation register (SAR);
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2012.2222837
Filename :
6352867
Link To Document :
بازگشت