A 86 MHz–12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS

Author

Borremans, Jonathan ; Vengattaramane, Kameswaran ; Giannini, Vito ; Debaillie, Björn ; Van Thillo, Wim ; Craninckx, Jan

Author_Institution

IMEC, Leuven, Belgium

Volume

45

Issue

10

fYear

2010

Firstpage

2116

Lastpage

2129

Abstract

A 86 MHz-12 GHz digital-intensive reconfigurable PLL frequency synthesizer is presented with 100 kHz to 2 MHz bandwidth. It leverages a 6 fJ/step 5.5 ps, 14b coarse-fine TDC and a 6-12 GHz dual-VCO set. Several simple calibration schemes are proposed that enable the proper performance of the highly efficient TDC in the PLL. The 0.28 mm² synthesizer, which is appropriate for use in a Software-Defined Radio, features noise cancellation and digital phase modulation and consumes less than 30 mW.

Keywords

CMOS digital integrated circuits; digital phase locked loops; frequency synthesizers; software radio; digital CMOS; digital phase modulation; digital-intensive reconfigurable PLL frequency synthesizer; dual-VCO set; frequency 100 kHz to 2 MHz; frequency 86 MHz to 12 GHz; noise cancellation; software-defined radios; time 5.5 ps; time-to-digital converters; CMOS integrated circuits; Calibration; Converters; Delay; Delay lines; Phase locked loops; Radiation detectors; 40 nm; Background calibration; CMOS; DAC; PLL; TDC; digital phase modulation; digital-intensive; digital-to-analog converter; fractional-N; time-to-digital converter;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2010.2063630

Filename

5584964