Title :
Rail-to-rail multiple-input min/max circuit
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
fDate :
1/1/1998 12:00:00 AM
Abstract :
The author presents a multiple-input min/max circuit technique that reduces the errors associated with previous analog implementations by combining a common-source voltage-mode configuration with a current-mode “winner takes all” circuit. The overall architecture exhibits linear complexity with the number of inputs. Both minimum and maximum two-input prototypes have been designed and built in a 2-μm CMOS process. The active area for each circuit is 650×100 μm2, and the total power dissipation is 0.8 mW from a single 5-V supply. Experimental results confirm rail-to-rail operation and sharp transition regions
Keywords :
CMOS analogue integrated circuits; analogue processing circuits; nonlinear filters; rectifying circuits; 0.8 mW; 2 micron; 5 V; CMOS process; common-source voltage-mode configuration; current-mode WTA circuit; multiple-input min/max circuit; rail-to-rail operation; two-input prototypes; winner takes all circuit; Application specific integrated circuits; Circuit testing; Current measurement; Digital circuits; Integrated circuit measurements; Integrated circuit technology; Monitoring; Solid state circuits; Very large scale integration; Voltage;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
