In-Plane Gate Transistors Fabricated by Using Atomic Force Microscopy Anode Oxidation

Author

Chung, Tung-Hsun ; Chen, Shu-Han ; Liao, Wen-Hsuan ; Lin, Shih-Yen

Author_Institution

Res. Center for Appl. Sci., Acad. Sinica, Taipei, Taiwan

Volume

31

Issue

11

fYear

2010

Firstpage

1227

Lastpage

1229

Abstract

An in-plane gate transistor fabricated by using the atomic force microscopy (AFM) lithography is investigated in this letter. By performing repeated oxidation and deoxidation procedures by using the AFM for four times, two V-shaped trenches are fabricated on the prepatterned mesas to isolate the electrical terminals of the device. Without exposing the channel region to the atmosphere, the device has exhibited standard transistor current-voltage characteristics in the 0-5 V range at room temperature, which may be advantageous for the future high-speed application of the device.

Keywords

atomic force microscopy; insulated gate field effect transistors; isolation technology; lithography; atomic force microscopy anode oxidation; atomic force microscopy lithography; channel region; deoxidation procedure; electrical terminal; in plane gate transistor; prepatterned mesa; temperature 293 K to 298 K; voltage 0 V to 5 V; Gallium arsenide; Lithography; Logic gates; Microscopy; Oxidation; Resistance; Transistors; Atomic force microscopy (AFM); in-plane gate transistors;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2010.2068273

Filename

5585701