Thermal-Mechanical Stress Modeling of Copper Chip-to-Substrate Pillar Connections

The thermal stress induced by the coefficient of thermal expansion mismatch between a silicon integrated circuit and an organic substrate is an important reliability issue for chip-to-substrate connections. Copper pillar chip-to-substrate connections, including solder-capped and all-copper pillars, are potential replacements for solder balls with underfill in flip-chip applications. The thermal stresses associated with copper pillar connections are a function of the shape, dimensions, and materials for copper pillars and their associated chip and substrate terminations. In this paper, the design of the copper pillar, chip-to-substrate connections has been studied using finite element analysis. A 3-D, half generalized plane deformation slice model is used to study the static thermal stress at elevated temperature. The design parameters include the shape and material of the pads at the terminus of the copper pillars and the nature of supporting collar around the pillar. The modeling results show that a chip-pad helps to lower the maximum thermal stress within the silicon die. Moreover, a supporting collar around the copper pillars serves to decrease the maximum thermal stress on the silicon die. A high-modulus polymer collar around the copper pillar serves to lower the stress at the pillar-to-chip-pad junction and increase the stress within the center of the pillar. The maximum thermal stress within the die was lowered from 160 MPa to 100 MPa by increasing the elastic modulus of the collar from 1.2 GPa to 11.8 GPa.