A novel high-performance CMOS 1-bit full-adder cell

Author

Shams, Ahmed M. ; Bayoumi, Magdy A.

Author_Institution

Center for Adv. Comput. Studies, Louisiana Univ., Lafayette, LA, USA

Volume

47

Issue

5

fYear

2000

fDate

5/1/2000 12:00:00 AM

Firstpage

478

Lastpage

481

Abstract

A novel 16-transistor CMOS 1-bit full-adder cell is proposed. It uses the low-power designs of the XOR and XNOR gates, pass transistors, and transmission gates. The cell offers higher speed and lower power consumption than standard implementations of the 1-bit full-adder cell. Eliminating an inverter from the critical path accounts for its high speed, while reducing the number and magnitude of the cell capacitances, in addition to eliminating the short circuit power component, account for its low power consumption. Simulation results comparing the proposed cell to the standard implementations show its superiority. Different circuit structures and input patterns are used for simulation. Energy savings up to 30% are achieved

Keywords

CMOS logic circuits; VLSI; adders; digital arithmetic; high-speed integrated circuits; integrated circuit design; logic design; low-power electronics; CMOS full-adder cell; XNOR gates; XOR gates; cell capacitances reduction; high speed operation; high-performance full-adder cell; low-power design; pass transistors; power consumption reduction; transmission gates; Adders; CMOS digital integrated circuits; Capacitance; Circuit simulation; Clocks; Digital signal processing; Energy consumption; Power supplies; Switching circuits; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.842117

Filename

842117