A Self-Aligned InGaAs HEMT Architecture for Logic Applications

In this paper, we present a novel self-aligned process for future III-V logic FETs. Using this process, we have demonstrated enhancement-mode 90-nm-gate-length InGaAs HEMTs with excellent logic figures of merit. We have carried out a detailed analysis of this device architecture to determine its future scaling capabilities. We find that, as the insulator is scaled to achieve enhancement mode, the performance of the device is limited by degradation of the I _ON/I _OFF ratio due to gate leakage current. By use of TLM test structures, we have determined that the barrier resistance dominates the source resistance. We use a trilayer TLM model to predict the expected evolution of the contact resistance as it is scaled to realistic VLSI dimensions and find that the current technology results in resistance values that are two orders of magnitude higher than the desired target for sub-22-nm nodes. Using the model, we explore different options for device redesign. Both I _ON/I _OFF and source-resistance limitations imply that the use of a high-k gate dielectric will be required for future device implementations.