DocumentCode
1336300
Title
Designing in power-down test circuits
Author
Levy, Paul S.
Author_Institution
VLSI Technol. Inc., Tempe, AZ, USA
Volume
8
Issue
3
fYear
1991
Firstpage
31
Lastpage
35
Abstract
Built-in self-test circuitry that is active only during testing is described. The benefit of these types of circuits is that defects that are not uncovered within the test circuitry will not contribute to failures in the host´s ICs. Thus, the overall reliability of the IC in its targeted application should increase. Also, since the test circuitry is inactive, there will be less overall power consumption. Layout issues, simulation models, and interface/isolation considerations are discussed. Some general design guidelines are given.<>
Keywords
built-in self test; circuit reliability; integrated circuit testing; IC; built in self test circuitry; circuit layout; design guidelines; failures; interface/isolation considerations; power consumption; power-down test circuits; reliability; simulation models; Automatic testing; Circuit faults; Circuit testing; Costs; Integrated circuit testing; Logic testing; Manufacturing; Observability; Software testing; System testing;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/54.84241
Filename
84241
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