Efficient synthesiser for generation of fast parallel multipliers

An automatic generator is developed which can synthesise fixed-point multipliers of any bit accuracy with a speed performance comparable to other recently proposed full-custom results. This synthesiser performs global optimisation for the interconnection of compression elements to minimise the delay in the partial product summation tree (PPST). Also, the final adder following the PPST is carefully synthesised to reduce the cost without sacrificing the speed performance. Unlike the full-custom design method, our synthesiser is adaptable to any technology change. A significant improvement is achieved compared to the Synopsys synthesis results