Title :
Static CMOS latch-up considerations in HVIC design
Author :
Huang, Q. ; Amaratunga, Gehan A J ; Narayanan, E. M Sankara ; Milne, W.I.
Author_Institution :
Dept. of Eng., Cambridge Univ., UK
fDate :
4/1/1990 12:00:00 AM
Abstract :
Static latchup in CMOS devices placed on a thin epitaxial layer for high-voltage integrated circuits (HVIC) is investigated using SPICE. The layout configuration and substrate current have a major influence on CMOS latchup as compared with conventional CMOS structures. Special latchup conditions exist for NMOS devices adjacent to high-voltage devices due to an extra p-n-p-n path. The results suggest that the use of PMOS adjacent to the high-voltage is best suited, in terms of layout, to avoiding latchup conditions. It is also shown that the latchup of CMOS devices is improved by placing them in an n- epitaxial layer on a p- substrate
Keywords :
CMOS integrated circuits; electrical faults; electronic engineering computing; power integrated circuits; semiconductor device models; CMOS devices; HVIC design; NMOS devices; PMOS; SPICE; adjacent HV devices; high-voltage integrated circuits; layout configuration; models; n- epitaxial layer; p-n-p-n path; p- substrate; static latchup; substrate current; CMOS logic circuits; Costs; Epitaxial layers; Integrated circuit noise; Mirrors; SPICE; Semiconductor device modeling; Substrates; Temperature; Transistors;
Journal_Title :
Solid-State Circuits, IEEE Journal of
