Title :
Random pattern testability of memory control logic
Author_Institution :
Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
fDate :
3/1/1998 12:00:00 AM
Abstract :
This paper analyzes the random pattern testability of faults in the control logic of an embedded memory. We show how to compute exposure probabilities of these faults using mostly signal probability computations. We also show that the hardest memory control logic fault to detect is not necessarily the one with the lowest detection probability at the memory boundary
Keywords :
Markov processes; built-in self test; integrated circuit testing; integrated memory circuits; embedded memory; exposure probabilities; memory control logic; random pattern testability; signal probability computations; Built-in self-test; Computational modeling; Decoding; Fault detection; Feeds; Jacobian matrices; Logic testing; Pattern analysis; Random access memory; Read-write memory;
Journal_Title :
Computers, IEEE Transactions on
