Title :
A simplified architecture for module (2n+1) multiplication
Author_Institution :
Inst. of Comput. Technol., Acad. Sinica, Beijing, China
fDate :
3/1/1998 12:00:00 AM
Abstract :
The module (2n+1) multiplication is widely used in the computation of convolutions and in RNS arithmetic and, thus, it is important to reduce the calculation delay. This paper presents a concept of a module (2n+1) carry save adder (MCSA) and uses two MCSAs to perform the residue reduction. We also apply Booth´s algorithm to the module (2n+1) multiplication scheme in order to reduce the number of partial products. With these techniques, the new architecture reduces the multiplier´s calculation delay and is suitable for VLSI implementation for moderate and large n (n⩾16)
Keywords :
VLSI; adders; carry logic; convolution; residue number systems; Booth´s algorithm; RNS arithmetic; VLSI implementation; calculation delay; carry save adder; convolutions; module (2n+1) multiplication; partial products; Arithmetic; Computer architecture; Costs; Delay effects; Hardware; Roundoff errors; Throughput; Very large scale integration;
Journal_Title :
Computers, IEEE Transactions on
