Narrow-Width Effects on a Body-Tied Partially Depleted SOI MOSFET

Author

Valentin, Raphael ; Bertrand, Guillaume ; PUGET, Sophie ; Scheer, Patrick ; Juge, André ; Jaouen, Hervé ; Raynaud, Christine

Author_Institution

Lab. for Electron. & Inf. Technol. (LETI), Atomic Energy Comm. (CEA), Grenoble, France

Volume

58

Issue

11

fYear

2011

Firstpage

3793

Lastpage

3800

Abstract

In this paper, we present the investigation of narrow-width effects (NWEs) on partially depleted (PD) silicon-on-insulator (SOI) with different gate shape topologies. Based on dc/ac measurements and TCAD simulations, it shows detailed clarifications of body-tied-induced NWEs. The overall study demonstrates relationship between gate shape topologies, body-tied shape, and electrical width of the transistor. Provided physical-based analytical models are able to capture peak GM and C_GG as function of gate length, transistor width, physical gate-overlap width, and number of body tied. This results in improving the overall model accuracy of body contact and floating-body PD SOI MOSFETs.

Keywords

MOSFET; semiconductor device measurement; semiconductor device models; silicon-on-insulator; technology CAD (electronics); TCAD simulation; body contact; body-tied partially depleted SOI MOSFET; dc-ac measurement; electrical width; floating-body PD SOI MOSFET; gate length; gate shape topology; narrow-width effects; physical gate-overlap width; physical-based analytical model; silicon-on-insulator; transistor width; Contacts; Logic gates; MOSFET circuits; Shape; Silicon on insulator technology; Topology; Transistors; 65 nm; Body contact; MOSFET; body tied; narrow-width effects (NWEs); partially depleted (PD); silicon-on-insulator (SOI);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2011.2165283

Filename

6032736