Design of Memory Sense Amplifiers

A fundamental problem in the design of fast (4 to 6 ¿sec) word oriented memories using S-1 core material is the realization of a sensing amplifier which has the multitude of required properties. The sense amplifier is usually required to provide stable gain for bipolarity signals, to introduce a negligible delay into the signal path, to avoid dc level shift, to recover within a short time following the enable (or inhibit) noise, to provide a stable discrimination level, etc. Although many sense amplifier designs have appeared in the literature, none, to the authors´ knowledge, are eminently suitable for a 4- to 6-¿sec memory under the condition of ``worst case input pattern´´Â¿a long sequence of unipolarity pulses interspaced with ``blasts´´ of enable noise. The basic requirements for a sense amplifier suitable for a word oriented memory in conjunction with a required memory cycle are discussed. This newly developed sense amplifier and its operation and design are presented. Emphasis is placed on the evolution of the techniques and circuits presented, and several other approaches pursued during the design are also described. The authors also comment on possible future approaches to the sensing problem.