Improved bipolar transistor performance in CMOS by novel use of parasitic collector resistance

A design and layout technique which allows the use of the parasitic bipolar collector resistance as a load component in common emitter stages is discussed. This is achieved by using an extra collector contact in a force-sense arrangement. This removes the need for another load component, thereby reducing area, but more importantly the parasitic collector resistance is no longer limiting the transistor speed. The principle of operation is verified with fabricated transistors. The technique is applied to a bipolar/CMOS analog voltage comparator, and a speed improvement of a factor of three is obtained over a previous design in the same process which does not employ this technique. Simulation results for a voltage comparator designed by the technique, which resolved 12 b in 40 ns, are presented