Title :
Effects of Channel Width on Stress Enhancement for Damascene-Gate nFETs With Top-Cut Tensile-Stress Liner
Author :
Mayuzumi, Satoru ; Yamakawa, Shinya ; Wakabayashi, Hitoshi ; Tateshita, Yasushi ; Tsukamoto, Masanori ; Ohno, Terukazu ; Nagashima, Naoki
Author_Institution :
Semicond. Bus. Group, Sony Corp., Atsugi, Japan
Abstract :
This letter provides channel-stress behavior results induced by a local strain technique which consists of the process combination of a damascene-gate and top-cut tensile stress SiN liner for narrow channel-width nFETs using 3-D stress simulations and demonstrations. The dummy-gate removal, which is an intrinsic step in the damascene-gate process, is found to enhance tensile channel stress along the gate length at the edge of the channel beside the shallow trench isolation. In consequence of a mobility boost due to the high tensile stress, drain-current enhancement in the saturation is achieved for the damascene-gate nFETs with the narrow channel width and short gate length.
Keywords :
field effect transistors; damascene-gate nFET; drain-current enhancement; dummy-gate removal; stress enhancement; tensile channel stress; top-cut tensile-stress liner; Channel stress; damascene gate; gate last; high-$k$; metal gate; mobility; strain; stress simulation; top-cut stress liner;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2009.2035146