Title :
A simple and efficient measurement method for characterizing capacitance matrix of multilayer interconnection in VLSI
Author :
Mido, Tetsuhisa ; Ito, Hiroshi ; Asada, Kunihiro
Author_Institution :
VLSI Design & Educ. Center, Tokyo Univ., Japan
fDate :
5/1/2000 12:00:00 AM
Abstract :
A compact new test structure for direct extraction of components of the capacitance matrix for multilayer interconnections is presented. In this new method, each capacitive component in integrated structures is separately and directly obtained from measurement, and the total pads are kept to eight, independent of the size of the target matrix. As a result of evaluation of measurement errors caused by the asymmetry of structures, this new method can measure components of capacitance matrix with a precision of femto-farad order
Keywords :
VLSI; capacitance measurement; integrated circuit interconnections; integrated circuit measurement; measurement errors; VLSI; asymmetry; capacitance matrix; direct extraction; femto-farad precision; measurement errors; measurement method; multilayer interconnection; target matrix; total pads; Capacitance measurement; Circuit testing; Data mining; Delay estimation; Driver circuits; Indium tin oxide; Integrated circuit interconnections; Nonhomogeneous media; Parasitic capacitance; Very large scale integration;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
