DocumentCode :
1339277
Title :
A new TCAD-based statistical methodology for the optimization and sensitivity analysis of semiconductor technologies
Author :
Williams, S. ; Varahramyan, K.
Author_Institution :
Electr. Eng. Program, Louisiana Tech. Univ., Ruston, LA, USA
Volume :
13
Issue :
2
fYear :
2000
fDate :
5/1/2000 12:00:00 AM
Firstpage :
208
Lastpage :
218
Abstract :
A new TCAD-based statistical methodology for the optimization and sensitivity analysis of semiconductor technologies has been developed and demonstrated on a 0.18-μm SOI CMOS process. Two new screening techniques applicable to deterministic systems (Lenth´s test and normal probability plots) were introduced and compared with correlation analysis. The graphical nature of the new techniques provided easier analysis of the screening results by clearly displaying which process factors surpass predefined significance limits. A multiresponse steepest ascent analysis was developed to locate regions of improved process performance before beginning response surface experimentation. To perform the analysis, a composite function representing the response criteria was constructed using desirability functions and incorporated within the steepest ascent methodology. Locating the region of improved performance allowed smaller experimental designs to be used for the response study significantly improving model accuracy. The response models were used to optimize the SOI CMOS process and perform sensitivity analyzes on both the baseline and optimized processes. Optimization resulted in a 15% increase in Idsat without violating any other criteria. The results of the sensitivity analyzes, which showed the greatest benefit from the increased model accuracy, indicated no conspicuous device performance degradation caused by anticipated manufacturing variations
Keywords :
CMOS integrated circuits; design for manufacture; integrated circuit modelling; process monitoring; sensitivity analysis; silicon-on-insulator; statistical analysis; technology CAD (electronics); Lenth´s test; SOI CMOS process; TCAD-based statistical methodology; composite function; desirability functions; deterministic systems; device performance degradation; model accuracy; multiresponse steepest ascent analysis; normal probability plots; optimization; response criteria; screening techniques; semiconductor technologies; sensitivity analysis; significance limits; CMOS process; CMOS technology; Optimization methods; Performance analysis; Probability; Response surface methodology; Semiconductor device modeling; Sensitivity analysis; Statistical analysis; System testing;
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/66.843636
Filename :
843636
Link To Document :
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