The study and proposal for improvement the multilane operation of SpaceFibre protocol

SpaceFibre protocol, which is developed by European Space Agency as a standard protocol to communicate between payloads in satellite network, adopts multi-lane technique to increase transfer rate by using multiple physical links. To realize high transfer rate in which the multi-lane technique is needed, e.g. 20Gbps, FPGAs or ASICs devices to process the SpaceFibre protocol needs to increase operating frequency or to extend processing data width at one clock cycle. The later way is generally adapted for giga bps class transfer system since the operating frequency of FPGAs and ASICs for space systems is relatively lower than these devices for commercial systems. It is important to consider a length of data to be processed when extending the processing data width at one clock cycle. In the SpaceFibre protocol, it is effective to design processing device with 32-bits data width, because the minimum unit of transmitting/receiving data width is 32-bits. For example, however, if the width of data bus is assumed to 64-bits, it is possible that frame boundaries between leading data frame and following data frame is appeared in the middle of data bus. In this case, two frames have to be processed at the same time and it causes increase of complexity for processing and increase of circuit size. To mitigate the complexity, we change the frame length to be aligned with the utilized lane number at the framing layer. In this paper, we report the method for alignment of frame length and its evaluation results.