• DocumentCode
    1340152
  • Title

    Reliability Implications of Bias-Temperature Instability in Digital ICs

  • Author

    Park, Sang Phill ; Kang, Kunhyuk ; Roy, Kaushik

  • Author_Institution
    Purdue Univ., West Lafayette, IN, USA
  • Volume
    26
  • Issue
    6
  • fYear
    2009
  • Firstpage
    8
  • Lastpage
    17
  • Abstract
    Bias temperature instability (BTI) is one of the major reliability challenges in nanoscale CMOS technology. This article investigates the severity of such degradation in logic and memory circuits. The simulation results reveal that BTI poses severe constraints on reliable memory design, especially in the presence of random process variations.
  • Keywords
    CMOS integrated circuits; integrated circuit design; integrated circuit reliability; logic circuits; bias-temperature instability; digital IC; logic circuits; memory circuits; nanoscale CMOS technology; random process variations; reliability implications; Circuit simulation; Degradation; Logic circuits; MOSFETs; Niobium compounds; Silicon; Stress; Temperature; Titanium compounds; Transistors; NBTI; PTM; RDF; Si-H bonds; bias-temperature instability; design and test; memory array; nanoscale technology; random logic; random process variation;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2009.154
  • Filename
    5340383
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1340152