DocumentCode
1340160
Title
Modeling Low-k Dielectric Breakdown to Determine Lifetime Requirements
Author
Bashir, Muhammad ; Milor, Linda
Author_Institution
Georgia Inst. of Technol., Atlanta, GA, USA
Volume
26
Issue
6
fYear
2009
Firstpage
18
Lastpage
27
Abstract
Low-k dielectric breakdown and stress migration have emerged as new sources of wearout for on-chip interconnect. This article analyzes statistical data from a 45-nm test chip and constructs a methodology to determine the lifetime of low-k materials under process variations.
Keywords
electric breakdown; low-k dielectric thin films; low-k dielectric breakdown; low-k materials; on-chip interconnect; statistical data; stress migration; Chemicals; Copper; Dielectric breakdown; Dielectric materials; Dielectric measurements; Electric breakdown; Geometry; Stress; Testing; Voltage; design and test; line width variation; low-k dielectrics; semiconductor reliability;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.2009.151
Filename
5340384
Link To Document