DocumentCode
1340193
Title
Reliability Challenges and System Performance at the Architecture Level
Author
Rivers, Jude A. ; Kudva, Prabhakar
Author_Institution
Thomas J. Watson Res. Center, IBM, Hawthorne, TX, USA
Volume
26
Issue
6
fYear
2009
Firstpage
62
Lastpage
73
Abstract
The challenge for future reliable systems is to provide protection against all types of errors while delivering performance and managing power and complexity. This article gives an overview of reliability challenges, and describes techniques and methodologies that can be used to achieve error detection and correction in a complex, high-performance system.
Keywords
computer architecture; error compensation; error correction; error detection; performance evaluation; reliability theory; architecture level; complex system; error correction; error detection; errors protection; high performance system; reliability challenge; system performance; CMOS technology; Error correction; Frequency; Logic; Power system reliability; Random access memory; System performance; Temperature; Voltage; Wire; architecture; design and test; fault detection; performance; permanent fault; power; reliability; soft error;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.2009.153
Filename
5340388
Link To Document