Synchronizing the IEEE 1149.1 test access port for chip level testability

IEEE STD 1149.9 is a widely accepted testability standard in the industry. Although its mandatory provisions focus narrowly on board level assembly verification testing, primarily via the boundary-scan register, its test access port (TAP) and many optional provisions make the standard usable for a much broader range of applications. Since its inception, numerous extensions and applications have been proposed that allow the standard´s TAP to be used at the system level for general system-level test and maintenance tasks and at the chip level for accessing chip-level testability features. Chip-level applications thus far have used the port for accessing the chip´s scan design or for simple triggering of on-chip built-in self-test features via the RUNBIST instruction. Applications requiring general access to chipwide testability features that operate at the full chip-clock rate have been rare, primarily because of one of the standard´s basic tenets-namely, its dedicated test clock. This strategy enhances the test port to let it operate with two clocks. One is used while accessing IEEE 1149.1-compliant features, the other while accessing chip manufacturing test features