Zero-crossing-based 8-bit 100 MS/s pipelined analogue-to-digital converter with offset compensation

A zero-crossing-based 8-bit 100 MS/s pipelined analogue-to-digital converter (ADC) using an offset compensation method is presented. The ADC has been fabricated by 0.18 m CMOS process with a die area of 0.69 mm². While the common-mode voltage tracking circuit is turned on, for an input signal of 41 MHz with the sampling rate of 100 MS/s, the measured SNDR is 43.82 dB with effective number of bits 7.0-bit, the DNL 0.79-LSB and the INL 1.24-LSB. The power is 8 mW at a supply voltage of 1.8 V.