• DocumentCode
    1340426
  • Title

    Zero-crossing-based 8-bit 100 MS/s pipelined analogue-to-digital converter with offset compensation

  • Author

    Lee, H.-Y.

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • Volume
    5
  • Issue
    5
  • fYear
    2011
  • fDate
    9/1/2011 12:00:00 AM
  • Firstpage
    411
  • Lastpage
    417
  • Abstract
    A zero-crossing-based 8-bit 100 MS/s pipelined analogue-to-digital converter (ADC) using an offset compensation method is presented. The ADC has been fabricated by 0.18 m CMOS process with a die area of 0.69 mm2. While the common-mode voltage tracking circuit is turned on, for an input signal of 41 MHz with the sampling rate of 100 MS/s, the measured SNDR is 43.82 dB with effective number of bits 7.0-bit, the DNL 0.79-LSB and the INL 1.24-LSB. The power is 8 mW at a supply voltage of 1.8 V.
  • Keywords
    CMOS digital integrated circuits; analogue-digital conversion; ADC; CMOS process; SNDR; bit rate 100 Mbit/s; common-mode voltage tracking circuit; frequency 41 MHz; offset compensation method; power 8 mW; size 0.18 mum; voltage 1.8 V; word length 7.0 bit; zero-crossing-based pipelined analogue-to-digital converter;
  • fLanguage
    English
  • Journal_Title
    Circuits, Devices & Systems, IET
  • Publisher
    iet
  • ISSN
    1751-858X
  • Type

    jour

  • DOI
    10.1049/iet-cds.2010.0329
  • Filename
    6034870
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1340426