Design and implementation of a high-throughput fully parallel complex-valued QR factorisation chips

Complex QR factorisation is a fundamental operation used in various applications such as adaptive beamforming and MIMO signal detection. In this paper, based on Givens rotation scheme, a high-throughput, fully parallel complex-valued QR factorisation (CQRF) design is presented. It features the lowest computing complexity in various factorising schemes and indicates no BER performance loss when applied to a MIMO signal detection system. Via carefully plotted scheduling, one CQRF computation can be completed in eight clock cycles. In hardware design, a low complexity and look-up-table-free CORDIC algorithm is employed to implement the rotation operations. Further design optimisations, such as hardware sharing of common modules and reduction of register usage by shortening the variable´s life span, are also applied. Sized 2×2 and 4×4 chip designs largely following the IEEE 802.11n standard are developed. The implementation results in TSMC 0.18 um process technology show that the proposed 4×4 design, with a gate count of only 134.6 K, is capable of performing 15 M CQRFs per second. The measured power consumption is 196.3 mW at 120 MHz. Compound performance indexes such as area-time product and energy consumption per CQRF also indicate significant performance edges of the proposed designs.