DocumentCode
1340696
Title
An Evaluation of Several Two-Summand Binary Adders
Author
Sklansky, J.
Author_Institution
RCA Labs., Princeton, N. J.
Issue
2
fYear
1960
fDate
6/1/1960 12:00:00 AM
Firstpage
213
Lastpage
226
Abstract
Five fairly representative members of the class of two-summand binary adders are described and evaluated. Hopefully, this will help the development of more general approaches to computer subsystems evaluation. The adders are evaluated on the basis of three quantities: the number of two-input AND gates and OR gates, G; the gate-normalized addition time, ¿; and the number of bits, n, in each summand. Three plausible formulas for computational efficiency, ¿, are postulated, and plotted vs n for the five adders. Based on a comparison of the resulting curves, the following efficiency formula seems preferable: ¿ = n/¿log2G. Of the five adders considered, the new ``conditional-sum adder´´ is best by the above formula when n¿ 3. Other adders, however, are shown to be superior when the assumptions underlying the evaluation of G and ¿ are changed. The evaluation is found to have several limitations; these are discussed. Curves of G and ¿ vs n are given. It is suggested that these curves can serve as raw data for other evaluations, so that various evaluation methods may be compared.
Keywords
Arithmetic; Art; Computational efficiency; Control equipment; Logic design; Microprogramming; Performance evaluation; Senior members; Weapons;
fLanguage
English
Journal_Title
Electronic Computers, IRE Transactions on
Publisher
ieee
ISSN
0367-9950
Type
jour
DOI
10.1109/TEC.1960.5219821
Filename
5219821
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