Constant-Weight Counters and Decoding Trees

A class of counters is described in which the number of 1´s in the flip-flops or register stages composing the counter remains constant as the counter advances from state to state. Simple digital circuit arrangements are described for the design of such counters, which may be used with a particular type of decoding tree as economical ring-type counters, to provide a separate output lead for each state. Some interesting theoretical questions concerning the minimization of these decoding trees are raised and partially answered. Finally, the costs of these counters are compared with one another, and with those of other types of counters, over a continuous range of values of the flip-flop/gate-input cost ratio.